1. Field of the Invention
The invention generally relates to integrated circuit structures and, more particularly, to integrated circuit structures that incorporate a silicon germanium film as an electrical contact and/or as a local interconnect between devices.
2. Description of the Related Art
It is often necessary to locally connect two or more devices below the wiring levels of an integrated circuit (i.e., to provide local interconnects between devices within an integrated circuit). However, depending upon the technology and process flows used current methods of forming such local interconnects can be inefficient. Therefore, there is a need in the art for an improved local interconnect structure that can be used to connect two or more devices within an integrated circuit.
Additionally, solid-state circuits, including memory devices and flip-flops, are susceptible to upset by ionizing radiation, noise and other sources. These upsets are known as soft errors because information is lost but the circuit is not damaged. Thus, soft errors reflect system reliability as opposed to permanent system failure. For example, in a static random access memory (SRAM) cell, source and diffusion nodes can accumulate charges from the surrounding environment (e.g., the packaging environment). Once a sufficient amount of charge is accumulated the state of the logic may flip at an undesired point in time causing a logical fault. The minimum charge required to flip the cell is referred to as the Qcrit and depends on the cell capacitance and supply voltage. As discussed in the recent article by Mukherjee et al. “The Soft Error Problem: An Architectural Perspective,” hpca, pp. 243-247, 11th International Symposium on High-Performance Computer Architecture (HPCA'05), 2005, techniques that have been used to reduce the soft error rate (SER) of SRAM cells have included increasing the cell capacitance and/or the supply voltage and creating radiation-hardened (rad-hard) cells. However, the SER of current state-of-the-art SRAM cells remains a concern due to significant area and power penalties associated with increasing capacitance in such rad-hard SRAM cells. Therefore, there is a need for an improved capacitor structure that can provide increased capacitance to devices, such as rad-hard SRAM cells, without significantly increasing area or power requirements.